EMSOFT 2004: 4th ACM International Conference on Embedded Software
Operating Systems
Remote Customization of Systems Code for Embedded Devices
Using Resource Reservation Techniques for Power-Aware Scheduling
An Experimental Analysis of the Effect of the Operating System on Memory Performance in Embedded Multimedia Computing
Verification
Model Based Estimation and Verification of Mobile Device Performance
Separation of Concerns: Overhead in Modeling and Efficient Simulation Techniques
Energy-aware systems
Practical PACE for Embedded Systems
Energy-Efficient, Utility Accrual Scheduling Under Resource Constraints for Mobile Embedded Systems
Binary Translation to Improve Energy Efficiency Through Post-Pass Register Re-Allocation
Scheduling
WRR-SCAN: a Rate-Based Real-Time Disk-Scheduling Algorithm
Scheduling within Temporal Partitions: Response-Time Analysis and Server Design
Programming Languages
A Typed Assembly Language for Real-Time Programs
Compiler-Assisted Demand Paging for Embedded Systems with Flash Memory
Garbage Collection for Embedded Systems
Formal Methods I
Reactive Process Networks
An Event Detection Algebra for Reactive Systems
System Design
Conservative Approximations for Heterogeneous Design
Exploiting Prescriptive Aspects: a Design Time Capability
Making Mechatronic Agents Resource-Aware in Order to Enable Safe Dynamic Resource Allocation
A Metrics System for Quantifying Operational Coupling in Embedded Computer Control Systems
Distributed Systems
Loose Synchronization of Event-Triggered Networks for Distribution of Synchronous Programs
Reuse of Software in Distributed Embedded Automotive Systems
Formal Methods II
A Model-Based Approach to Integrating Security Policies for Embedded Devices
Heterogeneous Reactive Systems Modeling: Capturing Causality and the Correctness of Loosely Time-Triggered Architectures (LTTA)
Formal Languages
Towards a Higher-Order Synchronous Data-Flow Language
Towards Direct Execution of Esterel Programs on Reactive Processors
A Methodology for Generating Verified Combinatorial Circuits
Defining and Translating a "Safe" Subset of Simulink/Stateflow Into Lustre
Timing Analysis
Approximation of the Worst-Case Execution Time using Structural Analysis
Multiple Process Execution in Cache Related Preemption Delay Analysis
An Approach for Integrating Basic Retiming and Software Pipelining
Reducing Program Image Size by Extracting Frozen Code and Data